Welcome to the JHDL® WWW Site. Check back often for JHDL® news
JHDL is a set of FPGA CAD tools
developed at Brigham Young University's
Configurable Computing Laboratory
that allows the user to design the structure and layout of a circuit,
debug the circuit in simulation, netlist and interface for bit-stream
synthesis, and so forth. It is an exploratory attempt to identify the
key features and functionality of good FPGA tools.
New! Quick Start Guide --
Four easy steps which ensure a smooth
beginning with JHDL.
Java JHDL Downloads
The latest version of JHDL,
release 0.3.45, is now available for download. The website search
engine has been reindexed to reflect these latest changes.