Brigham Young University

Main Menu

. /
  | Mailing List | BYU Configurable Computing Laboratory | Bug Reports |

A Simple Array Multiplier Applet

A simple applet has been created to demonstrate how JHDL can be used to generate, simulate and netlist circuit modules for FPGAs. This specific example generates an Array Multiplier circuit that is found within the JHDL module generator library. Instructions for operating with the Applet are shown below the Applet window.

Array Multiplier Demo Instructions

To experiment with this module generator applet, perform the following steps:
  1. Building the Array Multiplier
    • Select the parameters of the Array Multiplier module generator that you would like. You can select the widths of the multiplier, multiplicand as well as the product. In addition, you can make the multiplier signed or unsigned and control the depth of the pipeline (the pipeline depth indicates how many levels of registers are inserted into the multiplier).
    • When you have selected your parameters, press the Build button. This will construct the multiplier as you have selected and display a schematic of the multiplier in the schematic panel.
    • After building a circuit, you can always go back and modify the module parameters and press Build to recreate a circuit.
  2. Viewing the Array Multiplier Circuit
    • Once the circuit has been created, you can view the structure of the circuit in the schematic window that was created for you. You can pan around the top-level circuit using the scroll bars.
    • You can push into the schematic by double-clicking on any of the circuit cells. This will create and display a new schematic window. Tabs are shown below the schematics to select between the various open schematic windows.
  3. Simulating the Array Multplier Circuit
    • Once the array multiplier has been constructed, you can simulate the circuit by pressing the Cycle button. This will issue a single clock on the design and display the values of the wires/registers within the schematic windows.
    • You can change the values of the x and y inputs using the text boxes in the applet. You can also enable/disable the auto increment mode of the inputs. The default mode is to auto increment the x and y after each clock cycle.
    • The simulation can be reset by pressing the Reset button. This will reinitialize the state of the simulation.
  4. Viewing signal waveforms
    • You can view a waveform for a signal by double-clicking on any wire in the schematic. This will open a new "Waves Viewer" window over the schemati (use the tabs to select between the schematic and waves windows). Note that the waveform window does not display the signal name by default. Move the window panel bars to the left of the panel to view the signal names and values.
    • Any number of wires can be viewed by double clicking on the appropriate schematic wire.
  5. Generating an EDIF circuit netlist
    • You can generate an EDIF netlist of the circuit by pressing the Netlist button. This will open a new window and display the netlist in a scrollable text window.
  6. Notes on the STATS of the circuit
    • Before the circuit is built the statistics of the circuit are not available(NA). After the circuit is built the statistics will appear. The # LUTs is the total number of LUTs that this circuit will map to and is a rough estimation of the size of the circuit when placed on an FPGA. The Cycle Time will give the maximum number of LUTs for the worst case propigation delay. The actual time is dependant on routing and the specific FPGA used. The Latency will tell you the number of clock cycles it takes to get the output of the circuit after the inputs have been set.
Copyright © Brigham Young University 2002
JHDL is licensed under this licence