A simple applet has been created to demonstrate how JHDL can be used to generate, simulate
and netlist circuit modules for FPGAs. This specific example generates
an Digit Serial Multiplier circuit. Also a parellel to digit serial
converter is used on one input and a digit serial to parellel
converter is used on the output.
Instructions for operating with the Applet are shown below the Applet window.
Digit Serial Multiplier Demo Instructions
To experiment with this module
generator applet, perform the following steps:
Building the Digit Serial Multiplier
Select the parameters of the Digit serial Multiplier
that you would like. You can select the widths of the multiplier inputs,
as well as the product width. You also to set the constant to
be used in the multiplier.
When you have selected your parameters, press the Build
button. This will construct the multiplier as you have selected and
display a schematic of the multiplier in the schematic panel.
After building a circuit, you can always go back and modify the
module parameters and press Build to recreate a circuit.
Viewing the Digit Serial Multiplier Circuit
Once the circuit has been created, you can view the structure of
the circuit in the schematic window that was created for you. You can
pan around the top-level circuit using the scroll bars.
You can push into the schematic by double-clicking on any of the
circuit cells. This will create and display a new schematic window.
Tabs are shown below the schematics to select between the various open
schematic windows.
Simulating the Digit Serial Multplier Circuit
Once the digit serial multiplier has been constructed, you can simulate
the circuit by pressing the Cycle button. This will issue a
single clock on the design and display the values of the
wires/registers within the schematic windows.
You can change the values of the x and y inputs using the text
boxes in the applet. You can also enable/disable the auto simulate
mode of the inputs. The default mode is to auto simulate the
multiplier which increments the inputs and asserts the start bit
for one cycle and then cycles until the output is ready. Then the
inputs are incremented, and the start bit is again asserted.
The simulation can be reset by pressing the Reset
button. This will reinitialize the state of the simulation.
Viewing signal waveforms
You can view a waveform for a signal by double-clicking on any
wire in the schematic. This will open a new "Waves Viewer" window over
the schematic window (use the tabs to select between the schematic
and waves windows).
Any number of wires can be viewed by double clicking on the
appropriate schematic wire.
Generating an EDIF circuit netlist
You can generate an EDIF netlist of the circuit by pressing the
Netlist button. This will open a new window and display the
netlist in a scrollable text window.
Notes on the STATS of the circuit
Before the circuit is built the statistics of the circuit are not
available(NA). After the circuit is built the statistics will
appear. The # LUTs is the total number of LUTs that this circuit
will map to and is a rough estimation of the size of the circuit
when placed on an FPGA. The Cycle Time will give the
maximum number of LUTs for the worst case propigation delay. The
actual time is dependant on routing and the specific FPGA used.
The Latency will tell you the number of clock cycles it takes to
get the output of the circuit after the inputs have been set.
