A simple applet has been created to demonstrate how JHDL can be used to generate, simulate
and netlist circuit modules for FPGAs. This specific example generates
an Virtex KCM Multiplier
circuit.
Instructions for operating with the Applet are shown below the Applet window.
KCM Multiplier Demo Instructions
To experiment with this module
generator applet, perform the following steps:
Building the KCM Multiplier
Select the parameters of the Constant Coefficient Multiplier module generator
that you would like. You can select the widths of the multiplier input,
as well as the constant and product. You also to set the constant to
be used in the multiplier. In addition, you can make the
multiplier signed or unsigned, make the constant signed or unsigned,
and set it to be fully pipelined.
When you have selected your parameters, press the Build
button. This will construct the multiplier as you have selected and
display a schematic of the multiplier in the schematic panel.
After building a circuit, you can always go back and modify the
module parameters and press Build to recreate a circuit.
The License Field
The license field gives the user different privledges for
viewing and simulating the circuit depending on the level of thier
license. This is an example of how the applet can be used to
protect the IP by offering different levels of visibility from the
provider to the user depending on their licensing agreement.
Changes to the license field will take place when the build
button is pressed.
The different levels provided in this example are:
Stats: This level provides only the statistics of
the circuit offering no information on the internals of the
circuit and no ability to simulate the circuit.
Sim: This level of visibility gives the user
permision to simulate the circuit and see how the output
values are updated.
Schem_1: This level of visibility allow the user to
see the top level schematic of the circuit. Basically it
looks like a black box, but the inputs and outputs can be seen.
Schem_2: This level of visibility adds an extra
level of visibility to the schematic viewer. The second
level of the schematic of the circuit will be visible.
Schem_a: All levels of the schematic will be visible
with this license.
Netlist: The Netlist button will be enabled and the
netlist can be created.
All: The user will be able to see all levels of the
schematic, simulate and create the netlist.
Viewing the KCM Multiplier Circuit
Once the circuit has been created, you can view the structure of
the circuit in the schematic window that was created for you. You can
pan around the top-level circuit using the scroll bars.
You can push into the schematic by double-clicking on any of the
circuit cells. This will create and display a new schematic window.
Tabs are shown below the schematics to select between the various open
schematic windows.
Simulating the KCM Multplier Circuit
Once the kcm multiplier has been constructed, you can simulate
the circuit by pressing the Cycle button. This will issue a
single clock on the design and display the values of the
wires/registers within the schematic windows.
You can change the values of the x and y inputs using the text
boxes in the applet. You can also enable/disable the auto increment
mode of the inputs. The default mode is to auto increment the
multiplier input after each clock cycle.
The simulation can be reset by pressing the Reset
button. This will reinitialize the state of the simulation.
Viewing signal waveforms
You can view a waveform for a signal by double-clicking on any
wire in the schematic. This will open a new "Waves Viewer" window over
the schematic window (use the tabs to select between the schematic
and waves windows).
Any number of wires can be viewed by double clicking on the
appropriate schematic wire.
Generating an EDIF circuit netlist
You can generate an EDIF netlist of the circuit by pressing the
Netlist button. This will open a new window and display the
netlist in a scrollable text window.
Notes on the STATS of the circuit
Before the circuit is built the statistics of the circuit are not
available(NA). After the circuit is built the statistics will
appear. The # LUTs is the total number of LUTs that this circuit
will map to and is a rough estimation of the size of the circuit
when placed on an FPGA. The Cycle Time will give the
maximum number of LUTs for the worst case propigation delay. The
actual time is dependant on routing and the specific FPGA used.
The Latency will tell you the number of clock cycles it takes to
get the output of the circuit after the inputs have been set.
