import byucc.jhdl.base.CellInterface;
import byucc.jhdl.base.Node;
import byucc.jhdl.base.Wire;
import byucc.jhdl.Logic.Logic;

/** A very basic JHDL design that can be used for simple
 * demonstrations and examples.
 * @author Anthony Slade */
public class AndNReg3Bit extends Logic {
  public static CellInterface[]
    cell_interface = {
      in("inA",3),
      in("inB",3),
      in("inC",3),
      out("out",3)
    };
  public AndNReg3Bit(Node parent, Wire a, Wire b, Wire c, Wire o) {
    super(parent);
    connect("inA", a);
    connect("inB", b);
    connect("inC", c);
    connect("out", o);

    reg_o(and(a,b,c),o);
  }
}