import byucc.jhdl.base.CellInterface;
import byucc.jhdl.base.Node;
import byucc.jhdl.base.Wire;
import byucc.jhdl.Logic.Logic;

/** Example JHDL design to demonstrate features of the
 * DynamicTestBench class.  See the script gatenreg.script for an
 * example of DynamicTestBench CLICommands to run to cause the design
 * to be built.
 * @author Anthony L. Slade */
public class GateNReg_NBit extends Logic {
  public static CellInterface[]
    cell_interface = {
      in("a","width"),
      in("b","width"),
      out("o","width"),
      param("width",INTEGER),
    };
  Wire a, b, o;
  public GateNReg_NBit(Node parent,
                       Wire a, Wire b, Wire o) {
    this(parent,a,b,o,"and");
  }
  public GateNReg_NBit(Node parent,
                       Wire a, Wire b, Wire o,
                       String gateType) {
    super(parent);
    int width = a.getWidth();
    bind("width",width);
    this.a = connect("a", a);
    this.b = connect("b", b);
    this.o = connect("o", o);

    Wire gateOutput;
    if      ( "and" .equalsIgnoreCase(gateType) ) gateOutput = and(a,b);
    else if ( "or"  .equalsIgnoreCase(gateType) ) gateOutput = or(a,b);
    else if ( "xor" .equalsIgnoreCase(gateType) ) gateOutput = xor(a,b);
    else if ( "nand".equalsIgnoreCase(gateType) ) gateOutput = nand(a,b);
    else if ( "nor" .equalsIgnoreCase(gateType) ) gateOutput = nor(a,b);
    else if ( "xnor".equalsIgnoreCase(gateType) ) gateOutput = xnor(a,b);
    else if ( "add" .equalsIgnoreCase(gateType) ) gateOutput = add(a,b);
    else if ( "notA".equalsIgnoreCase(gateType) ) gateOutput = not(a);
    else if ( "notB".equalsIgnoreCase(gateType) ) gateOutput = not(b);
    else if ( "a"   .equalsIgnoreCase(gateType) ) gateOutput = a;
    else if ( "b"   .equalsIgnoreCase(gateType) ) gateOutput = b;
    else if ( "one" .equalsIgnoreCase(gateType) ) gateOutput = constant(width,1);
    else   /* The default will just be zero */    gateOutput = constant(width,0);

    reg_o(gateOutput,o);
  }
}