(edif add
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2000 6 29 15 2 7)
      (program "BYU-CC's JHDL-EDIF netlister by Peter Bellows and Eric Blake"
        (version "JHDL.RELEASE.BRENT.6.28"))))
  (library add
    (edifLevel 0)
    (technology (numberDefinition (scale 1 (E 1 -12) (unit CAPACITANCE))))
    (cell gnd
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port GROUND  (direction OUTPUT))
        )
     ))
    (cell xor2
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port i0  (direction INPUT))
          (port i1  (direction INPUT))
          (port o  (direction OUTPUT))
        )
     ))
    (cell muxcy_l
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port di  (direction INPUT))
          (port ci  (direction INPUT))
          (port s  (direction INPUT))
          (port lo  (direction OUTPUT))
        )
     ))
    (cell xorcy
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port li  (direction INPUT))
          (port ci  (direction INPUT))
          (port o  (direction OUTPUT))
        )
     ))
    (cell fmap
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port i1  (direction INPUT))
          (port i2  (direction INPUT))
          (port i3  (direction INPUT))
          (port i4  (direction INPUT))
          (port o  (direction OUTPUT))
        )
     ))
    (cell muxcy
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port di  (direction INPUT))
          (port ci  (direction INPUT))
          (port s  (direction INPUT))
          (port o  (direction OUTPUT))
        )
     ))
    (cell add4
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port (array (rename a "a[0:3]") 4) (direction INPUT))
          (port (array (rename b "b[0:3]") 4) (direction INPUT))
          (port ci  (direction INPUT))
          (port (array (rename s "s[0:3]") 4) (direction OUTPUT))
          (port co  (direction OUTPUT))
        )
        (contents
          (instance xor0
            (viewRef view_1 (cellRef xor2)))
          (instance muxcy_l__0
            (viewRef view_1 (cellRef muxcy_l))
            (property RLOC (string "R1C0.S1") (owner  "JHDL")))
          (instance xorcy__0
            (viewRef view_1 (cellRef xorcy))
            (property RLOC (string "R1C0.S1") (owner  "JHDL")))
          (instance gnd__1
            (viewRef view_1 (cellRef gnd)))
          (instance gnd__3
            (viewRef view_1 (cellRef gnd)))
          (instance fmap__0
            (viewRef view_1 (cellRef fmap))
            (property RLOC (string "R1C0.S1") (owner  "JHDL")))
          (instance xor1
            (viewRef view_1 (cellRef xor2)))
          (instance muxcy_l__1
            (viewRef view_1 (cellRef muxcy_l))
            (property RLOC (string "R1C0.S1") (owner  "JHDL")))
          (instance xorcy__1
            (viewRef view_1 (cellRef xorcy))
            (property RLOC (string "R1C0.S1") (owner  "JHDL")))
          (instance gnd__5
            (viewRef view_1 (cellRef gnd)))
          (instance gnd__7
            (viewRef view_1 (cellRef gnd)))
          (instance fmap__1
            (viewRef view_1 (cellRef fmap))
            (property RLOC (string "R1C0.S1") (owner  "JHDL")))
          (instance xor2
            (viewRef view_1 (cellRef xor2)))
          (instance muxcy_l__2
            (viewRef view_1 (cellRef muxcy_l))
            (property RLOC (string "R0C0.S1") (owner  "JHDL")))
          (instance xorcy__2
            (viewRef view_1 (cellRef xorcy))
            (property RLOC (string "R0C0.S1") (owner  "JHDL")))
          (instance gnd__9
            (viewRef view_1 (cellRef gnd)))
          (instance gnd__11
            (viewRef view_1 (cellRef gnd)))
          (instance fmap__2
            (viewRef view_1 (cellRef fmap))
            (property RLOC (string "R0C0.S1") (owner  "JHDL")))
          (instance xor3
            (viewRef view_1 (cellRef xor2)))
          (instance muxcy__0
            (viewRef view_1 (cellRef muxcy))
            (property RLOC (string "R0C0.S1") (owner  "JHDL")))
          (instance xorcy__3
            (viewRef view_1 (cellRef xorcy))
            (property RLOC (string "R0C0.S1") (owner  "JHDL")))
          (instance gnd__13
            (viewRef view_1 (cellRef gnd)))
          (instance gnd__15
            (viewRef view_1 (cellRef gnd)))
          (instance fmap__3
            (viewRef view_1 (cellRef fmap))
            (property RLOC (string "R0C0.S1") (owner  "JHDL")))

          (net (rename gnd__14 "gnd-14")
            (joined
              (portRef GROUND (instanceRef gnd__15))
              (portRef i4 (instanceRef fmap__3))))
          (net (rename gnd__12 "gnd-12")
            (joined
              (portRef GROUND (instanceRef gnd__13))
              (portRef i3 (instanceRef fmap__3))))
          (net (rename s_partial3 "s_partial3")
            (joined
              (portRef o (instanceRef xor3))
              (portRef s (instanceRef muxcy__0))
              (portRef li (instanceRef xorcy__3))
              (portRef o (instanceRef fmap__3))))
          (net (rename gnd__10 "gnd-10")
            (joined
              (portRef GROUND (instanceRef gnd__11))
              (portRef i4 (instanceRef fmap__2))))
          (net (rename gnd__8 "gnd-8")
            (joined
              (portRef GROUND (instanceRef gnd__9))
              (portRef i3 (instanceRef fmap__2))))
          (net (rename c2 "c2")
            (joined
              (portRef lo (instanceRef muxcy_l__2))
              (portRef ci (instanceRef muxcy__0))
              (portRef ci (instanceRef xorcy__3))))
          (net (rename s_partial2 "s_partial2")
            (joined
              (portRef o (instanceRef xor2))
              (portRef s (instanceRef muxcy_l__2))
              (portRef li (instanceRef xorcy__2))
              (portRef o (instanceRef fmap__2))))
          (net (rename gnd__6 "gnd-6")
            (joined
              (portRef GROUND (instanceRef gnd__7))
              (portRef i4 (instanceRef fmap__1))))
          (net (rename gnd__4 "gnd-4")
            (joined
              (portRef GROUND (instanceRef gnd__5))
              (portRef i3 (instanceRef fmap__1))))
          (net (rename c1 "c1")
            (joined
              (portRef lo (instanceRef muxcy_l__1))
              (portRef ci (instanceRef muxcy_l__2))
              (portRef ci (instanceRef xorcy__2))))
          (net (rename s_partial1 "s_partial1")
            (joined
              (portRef o (instanceRef xor1))
              (portRef s (instanceRef muxcy_l__1))
              (portRef li (instanceRef xorcy__1))
              (portRef o (instanceRef fmap__1))))
          (net (rename gnd__2 "gnd-2")
            (joined
              (portRef GROUND (instanceRef gnd__3))
              (portRef i4 (instanceRef fmap__0))))
          (net (rename gnd "gnd")
            (joined
              (portRef GROUND (instanceRef gnd__1))
              (portRef i3 (instanceRef fmap__0))))
          (net (rename c0 "c0")
            (joined
              (portRef lo (instanceRef muxcy_l__0))
              (portRef ci (instanceRef muxcy_l__1))
              (portRef ci (instanceRef xorcy__1))))
          (net (rename s_partial0 "s_partial0")
            (joined
              (portRef o (instanceRef xor0))
              (portRef s (instanceRef muxcy_l__0))
              (portRef li (instanceRef xorcy__0))
              (portRef o (instanceRef fmap__0))))
          (net (rename co "co")
            (joined
              (portRef o (instanceRef muxcy__0))
              (portRef co)))
          (net (rename s__0__ "s<0>")
            (joined
              (portRef o (instanceRef xorcy__0))
              (portRef (member s 0))))
          (net (rename s__1__ "s<1>")
            (joined
              (portRef o (instanceRef xorcy__1))
              (portRef (member s 1))))
          (net (rename s__2__ "s<2>")
            (joined
              (portRef o (instanceRef xorcy__2))
              (portRef (member s 2))))
          (net (rename s__3__ "s<3>")
            (joined
              (portRef o (instanceRef xorcy__3))
              (portRef (member s 3))))
          (net (rename ci "ci")
            (joined
              (portRef ci (instanceRef muxcy_l__0))
              (portRef ci (instanceRef xorcy__0))
              (portRef ci)))
          (net (rename b__0__ "b<0>")
            (joined
              (portRef i1 (instanceRef xor0))
              (portRef i2 (instanceRef fmap__0))
              (portRef (member b 0))))
          (net (rename b__1__ "b<1>")
            (joined
              (portRef i1 (instanceRef xor1))
              (portRef i2 (instanceRef fmap__1))
              (portRef (member b 1))))
          (net (rename b__2__ "b<2>")
            (joined
              (portRef i1 (instanceRef xor2))
              (portRef i2 (instanceRef fmap__2))
              (portRef (member b 2))))
          (net (rename b__3__ "b<3>")
            (joined
              (portRef i1 (instanceRef xor3))
              (portRef i2 (instanceRef fmap__3))
              (portRef (member b 3))))
          (net (rename a__0__ "a<0>")
            (joined
              (portRef i0 (instanceRef xor0))
              (portRef di (instanceRef muxcy_l__0))
              (portRef i1 (instanceRef fmap__0))
              (portRef (member a 0))))
          (net (rename a__1__ "a<1>")
            (joined
              (portRef i0 (instanceRef xor1))
              (portRef di (instanceRef muxcy_l__1))
              (portRef i1 (instanceRef fmap__1))
              (portRef (member a 1))))
          (net (rename a__2__ "a<2>")
            (joined
              (portRef i0 (instanceRef xor2))
              (portRef di (instanceRef muxcy_l__2))
              (portRef i1 (instanceRef fmap__2))
              (portRef (member a 2))))
          (net (rename a__3__ "a<3>")
            (joined
              (portRef i0 (instanceRef xor3))
              (portRef di (instanceRef muxcy__0))
              (portRef i1 (instanceRef fmap__3))
              (portRef (member a 3))))
        )
     ))
    (cell add
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port (array (rename a "a[0:3]") 4) (direction INPUT))
          (port (array (rename b "b[0:3]") 4) (direction INPUT))
          (port (array (rename q "q[0:3]") 4) (direction OUTPUT))
        )
        (contents
          (instance gnd__1
            (viewRef view_1 (cellRef gnd)))
          (instance adder__0
            (viewRef view_1 (cellRef add4)))

          (net (rename gnd "gnd")
            (joined
              (portRef GROUND (instanceRef gnd__1))
              (portRef ci (instanceRef adder__0))))
          (net (rename q__0__ "q<0>")
            (joined
              (portRef (member s 0) (instanceRef adder__0))
              (portRef (member q 0))))
          (net (rename q__1__ "q<1>")
            (joined
              (portRef (member s 1) (instanceRef adder__0))
              (portRef (member q 1))))
          (net (rename q__2__ "q<2>")
            (joined
              (portRef (member s 2) (instanceRef adder__0))
              (portRef (member q 2))))
          (net (rename q__3__ "q<3>")
            (joined
              (portRef (member s 3) (instanceRef adder__0))
              (portRef (member q 3))))
          (net (rename b__0__ "b<0>")
            (joined
              (portRef (member b 0) (instanceRef adder__0))
              (portRef (member b 0))))
          (net (rename b__1__ "b<1>")
            (joined
              (portRef (member b 1) (instanceRef adder__0))
              (portRef (member b 1))))
          (net (rename b__2__ "b<2>")
            (joined
              (portRef (member b 2) (instanceRef adder__0))
              (portRef (member b 2))))
          (net (rename b__3__ "b<3>")
            (joined
              (portRef (member b 3) (instanceRef adder__0))
              (portRef (member b 3))))
          (net (rename a__0__ "a<0>")
            (joined
              (portRef (member a 0) (instanceRef adder__0))
              (portRef (member a 0))))
          (net (rename a__1__ "a<1>")
            (joined
              (portRef (member a 1) (instanceRef adder__0))
              (portRef (member a 1))))
          (net (rename a__2__ "a<2>")
            (joined
              (portRef (member a 2) (instanceRef adder__0))
              (portRef (member a 2))))
          (net (rename a__3__ "a<3>")
            (joined
              (portRef (member a 3) (instanceRef adder__0))
              (portRef (member a 3))))
        )
     ))
  )
  (design ROOT
    (cellRef add
      (libraryRef add)))
)