.inputs reset writeReq readReq ;
.outputs latchAddr rw_ ack;    // Note that rw_ is asserted low!

.states init W1 W2 R;
.encodings default;

1-- -    init 010 ;   // Initialize circuit
000 init init 010 ;   // No request so don't change state
001 init R    110 ;   // Read request
01- init W1   110 ;   // Write request - note it takes priority over read
0-- R    init 011 ;   // Read done, signal ack and return
0-- W1   W2   010 ;   // Go to write state #2 and let address settle
0-- W2   init 001 ;   // Strobe rw_, assert ack and return