(edif ramtest
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2000 7 13 10 21 51)
      (program "BYU-CC's JHDL-EDIF netlister by Peter Bellows and Eric Blake"
        (version "JHDL.RELEASE.BRENT.7.13a"))))
  (library ramtest
    (edifLevel 0)
    (technology (numberDefinition (scale 1 (E 1 -12) (unit CAPACITANCE))))
    (cell (rename bufg "bufg")
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port i  (direction INPUT))
          (port o  (direction OUTPUT))
        )
     ))
    (cell (rename ram16x1s "ram16x1s")
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port d  (direction INPUT))
          (port we  (direction INPUT))
          (port a0  (direction INPUT))
          (port a1  (direction INPUT))
          (port a2  (direction INPUT))
          (port a3  (direction INPUT))
          (port o  (direction OUTPUT))
          (port wclk  (direction INPUT))
        )
     ))
    (cell (rename ramtest "ramtest")
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port d  (direction INPUT))
          (port we  (direction INPUT))
          (port (array (rename a "a[3:0]") 4) (direction INPUT))
          (port q  (direction OUTPUT))
          (port CLK  (direction INPUT))
        )
        (contents
          (instance ram16x1s__0
            (viewRef view_1 (cellRef ram16x1s))
            (property INIT (string "37a9") (owner  "JHDL")))

          (net (rename q "q")
            (joined
              (portRef o (instanceRef ram16x1s__0))
              (portRef q)))
          (net (rename a__0__ "a<0>")
            (joined
              (portRef a0 (instanceRef ram16x1s__0))
              (portRef (member a 3))))
          (net (rename a__1__ "a<1>")
            (joined
              (portRef a1 (instanceRef ram16x1s__0))
              (portRef (member a 2))))
          (net (rename a__2__ "a<2>")
            (joined
              (portRef a2 (instanceRef ram16x1s__0))
              (portRef (member a 1))))
          (net (rename a__3__ "a<3>")
            (joined
              (portRef a3 (instanceRef ram16x1s__0))
              (portRef (member a 0))))
          (net (rename we "we")
            (joined
              (portRef we (instanceRef ram16x1s__0))
              (portRef we)))
          (net (rename d "d")
            (joined
              (portRef d (instanceRef ram16x1s__0))
              (portRef d)))
          (net (rename CLK "CLK")
            (joined
              (portRef wclk (instanceRef ram16x1s__0))
              (portRef CLK)))
        )
     ))
  )
  (design ROOT
    (cellRef ramtest
      (libraryRef ramtest)))
)