import byucc.jhdl.base.*;
import byucc.jhdl.Logic.*;
import byucc.jhdl.Xilinx.Virtex.*;

public class tb_FullAdder extends Logic implements TestBench {
 
  static HWSystem hw;
  public static void main(String argv[]) {
    hw = new HWSystem();
    tb_FullAdder tb = new tb_FullAdder(hw);
    new cvt( tb );
  }

  private Wire a, b, sum, cout;
  
  public tb_FullAdder(Node parent) {
    super(parent);

    setDefaultTechMapper(new VirtexTechMapper(true));

    a = wire(1, "a");
    b = wire(1, "b");
    sum = wire(1, "sum");
    cout = wire(1, "cout");

    new FullAdder(this, a, b, gnd(), sum, cout);

  }

  public void reset() {
    a.put(this, 0);
    b.put(this, 0);
    cnt = 0;
  }
 
  int cnt = 0;
  public void clock() {
    cnt++;
    a.put(this, cnt & 0x1);
    b.put(this, (cnt>>1) & 0x1);
  }
}