byucc.jhdl.CSRC
Class mux_dpX

java.lang.Object
  extended bybyucc.jhdl.base.Nameable
      extended bybyucc.jhdl.base.Node
          extended bybyucc.jhdl.base.Cell
              extended bybyucc.jhdl.base.Structural
                  extended bybyucc.jhdl.Logic.LogicGates
                      extended bybyucc.jhdl.Logic.LogicStatic
                          extended bybyucc.jhdl.Logic.Logic
                              extended bybyucc.jhdl.CSRC.CSRCCL
                                  extended bybyucc.jhdl.CSRC.mux_dpX
All Implemented Interfaces:
BooleanFlags, Clockable, PreDefinedSchematic, byucc.jhdl.base.Propagateable, TreeListable

public final class mux_dpX
extends CSRCCL
implements PreDefinedSchematic

Generic width 2-1 Mux. i_2 is select, and a 1 on select gives you i_0 (odd but that's how it works).


Field Summary
static CellInterface[] cell_interface
           
static java.lang.String cellname
          The static cellname (netlist reference name) for mux_dpX
protected  int width
          The port interface for: mux_dpX i_0 : in ("gw") i_1 : in ("gw") i_2 : in (1) o_0 : out ("gw") parameter: "gw" (INTEGER).
 
Fields inherited from class byucc.jhdl.CSRC.CSRCCL
implicit_interface
 
Fields inherited from class byucc.jhdl.Logic.Logic
ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF
 
Fields inherited from class byucc.jhdl.Logic.LogicGates
tech_mapper
 
Fields inherited from class byucc.jhdl.base.Cell
BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD
 
Fields inherited from interface byucc.jhdl.apps.Viewers.Schematic.PreDefinedSchematic
PreDefinedSchematic_ADD, PreDefinedSchematic_ADDSUB, PreDefinedSchematic_AND, PreDefinedSchematic_BUF, PreDefinedSchematic_CONST, PreDefinedSchematic_GEN, PreDefinedSchematic_GND, PreDefinedSchematic_INC, PreDefinedSchematic_INV, PreDefinedSchematic_MUX, PreDefinedSchematic_NAND, PreDefinedSchematic_NOR, PreDefinedSchematic_OR, PreDefinedSchematic_PULLDOWN, PreDefinedSchematic_PULLUP, PreDefinedSchematic_REG, PreDefinedSchematic_SHL, PreDefinedSchematic_SHR, PreDefinedSchematic_TBUF, PreDefinedSchematic_VCC, PreDefinedSchematic_XNOR, PreDefinedSchematic_XOR
 
Fields inherited from interface byucc.jhdl.base.BooleanFlags
ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE
 
Constructor Summary
protected mux_dpX(Node parent)
          Used only by child classes to pass up the parent cell.
  mux_dpX(Node parent, ArgBlockList abl)
          Constructs a new mux_dpX, connecting its ports as given by the String-Wire pairs in the ArgBlockList.
protected mux_dpX(Node parent, java.lang.String name)
          Used only by child classes to pass up the parent cell and instance name.
  mux_dpX(Node parent, java.lang.String instanceName, ArgBlockList abl)
          Constructs a new mux_dpX, connecting its ports as given by the String-Wire pairs in the ArgBlockList.
  mux_dpX(Node parent, java.lang.String instanceName, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3)
          Constructs a new mux_dpX, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.
  mux_dpX(Node parent, java.lang.String s0, Wire w0, java.lang.String s1, Wire w1, java.lang.String s2, Wire w2, java.lang.String s3, Wire w3)
          Constructs a new mux_dpX, connecting each Wire to the port whose name is given by the accompanying String parameter
  mux_dpX(Node parent, java.lang.String instanceName, Wire i_0, Wire i_1, Wire i_2, Wire o_0)
          Constructs a new mux_dpX.
  mux_dpX(Node parent, Wire i_0, Wire i_1, Wire i_2, Wire o_0)
          Constructs a new mux_dpX.
 
Method Summary
 boolean cellInterfaceDeterminesUniqueNetlistStructure()
          When false, the default behavior of this method, each cell will list itself separately in a netlist, guaranteeing that the netlist will not have invalid data at the expense of a larger file-size.
 java.lang.String getCellName()
          Access the cell name associated with a derived class.
static void main(java.lang.String[] argv)
           
static void test()
           
 int type()
          This method returns one of the predefined schematic constants to identify the type of this cell.
 
Methods inherited from class byucc.jhdl.CSRC.CSRCCL
connectImplicitPorts
 
Methods inherited from class byucc.jhdl.Logic.Logic
clockDriver, clockDriver, connect_implicit_ports, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight
 
Methods inherited from class byucc.jhdl.Logic.LogicStatic
add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor
 
Methods inherited from class byucc.jhdl.Logic.LogicGates
add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, nor, not_o, not_o, not, not, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o, or_o,