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java.lang.Objectbyucc.jhdl.base.Nameable
byucc.jhdl.base.Node
byucc.jhdl.base.Cell
byucc.jhdl.base.Structural
byucc.jhdl.Logic.LogicGates
byucc.jhdl.Logic.LogicStatic
byucc.jhdl.Logic.Logic
byucc.jhdl.contrib.modgen.Cordicl
Generic width linear CORDIC unit for Xilinx XC4000. The CORDIC is parameterized with respect to wordsize, number of iterations, pipeline depth, and CORDIC function.
For an introduction to CORDIC processors, see Andraka, Ray. A survey of CORDIC algorithms for FPGA based computers.
| Field Summary | |
static CellInterface[] |
cell_interface
|
static java.lang.String |
cellname
|
static int |
ROTATIONAL
|
static int |
UNIFIED
|
static int |
VECTOR
|
| Fields inherited from class byucc.jhdl.Logic.Logic |
ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF |
| Fields inherited from class byucc.jhdl.Logic.LogicGates |
tech_mapper |
| Constructor Summary | |
Cordicl(Node parent,
int cordicmode,
boolean registered,
int num_iter,
int pipe_depth,
Wire clk_en,
Wire vec,
Wire xin,
Wire yin,
Wire zin,
Wire xout,
Wire yout,
Wire zout)
Constructor for CORDIC unit |
|
| Method Summary | |
void |
clock()
Users define synchronous behavior in this method using standard JHDL constructs. |
static int[] |
compute(int width,
int num_iterations,
int cordicmode,
int x,
int y,
int z,
int v)
Compute implements the behavior of the CORDIC for behavioral modelling of the circuit |
boolean |
defaultSimulationModelIsBehavioral()
The default simulation model is behavioral. |
java.lang.String |
getCellName()
Access the cell name associated with a derived class. |
void |
propagate()
Users defined propagatable behavior using standard JHDL constructs. |