byucc.jhdl.contrib.modgen
Class arrayMult

java.lang.Object
  byucc.jhdl.base.Nameable
      byucc.jhdl.base.Node
          byucc.jhdl.base.Cell
              byucc.jhdl.base.Structural
                  byucc.jhdl.Logic.LogicGates
                      byucc.jhdl.Logic.LogicStatic
                          byucc.jhdl.Logic.Logic
                              byucc.jhdl.contrib.modgen.arrayMult

All Implemented Interfaces:

BooleanFlags, Clockable, byucc.jhdl.base.Propagateable, TreeListable, UserDefinedSchematic

public class arrayMult

extends Logic

implements UserDefinedSchematic

Variable width array multiplier with the option of signed or unsigned multiply and generic pipeline depth.

Copyright (c) 1998-2000 Brigham Young University. All rights reserved. Reproduction in whole or in part in any form or medium without express permission of Brigham Young University is prohibited.

As seen in the diagram, the multiplier will multiply the two inputs on the buses x and y and produce a product outputted on the pout bus. If the width of the pout (product) bus is less than the sum of the width of the x and y buses, then the most significant bits will be outputted with the least significant bits truncated off.

Other characterics of note:

The multiplicand and the multiplier must be as least 3 bits. Currently the behavioral model will be valid if the sum of the bit widths of the multiplicand and the multiplier does not exceed 64. The multiplier structurally should be valid for input widths up to 64 bits (although any case where either of the input wire widths are greater than 32 bits or the output wires width is greater than 64 bits have not been tested thouroughly and are not guaranteed to be correct).

The width of x determines the height and the width of y determines the width of the multiplier (see technology section below for exact sizes).

If the clk_en input is passed a "null" then no clk_en net will be created.

Implementation

All Technologies

This is a standard array multiplier built using carry-propagate adders (because of the low-latency carry-chain available in Xilinx FPGAs).

Pipelining and Latency

The pipelining of this module is implemented based on the assumption that every pipeline stage should be balanced. Thus the pipedepth parameter of this divider does NOT represent the latency of the divider but the frequency of a pipeline register.
pipedepth=0 means fully-combinational multiplier
pipedepth=1 means fully-pipelined multiplier (one pipeline register per logic stage).
pipedepth=2 means place a pipeline register every other stage
pipedepth=3 means place a pipeline register every third stage
etc...
If there is a shorter stage it will be the first stage in the multiplier in order to allow more time for inputs to arrive. Also note that no input registering is done and therefore must be done by the user if desired. The latency corresponding to a particular multiplier configuration can be queried using the static latency method or by using the getLatency method once a multiplier has been constructed.

The number of pipeline stages (registers between multiplier stages) can be calculated by following formula:
(Y=width(y) P=pipedepth and the operator '/' is an integer divide (throw away remainder))
if P=0: pipline registers=0
otherwise: pipeline registers= ((Y-1)/P) + 1

Xilinx XC4000

Area and Placement

Enter parameters below to find the area and placement of a specific sized multiplier (units are in CLBs). Note that the dimensions count any CLB that is partially used (i.e. the flip-flops in the CLB may be used but not the LUTs and carryLogic). An important note is that if the clock enable pin is tied high, the Xilinx placement tools will optimize this net away, thus eliminating the potential critical path of a clock enable net.

NOTE: To minimize area and speed for a pipelined divider (pipedepth > 0) one should make the width of the y input less than that of the x input. For example, if you had a 18x8 multiplier pass the 8-bit wire into the y input and the 18-bit wire into the x input (if you do it the other way, the area about doubles when pipedepth is 2). A warning message will be given if a multiplier with the width of the y input is greater than the width of the x input. If this warning message is not desired one can set the static variable disableWarning to true (i.e. arrayMult.disableWarning = true; ).

Fill in the fields below and press compute

Input X Width (must be >= 3, default 3):

Input Y Width (must be >= 3, default 3):

Number of Pipeline Stages (default 0):
0 = purely combinational
1 = fully pipelined (pipeline register after every adder stage)
2 = half-pipelined (pipeline register after every other adder stage)

Signed: Signed

Part Size (in CLBs) :

Xilinx Virtex

Area and Placement

Placement in Virtex is almost identical to XC4000 except for a few minor differences. Same as XC4K (use form above to query size) except when fully-combinational (pipedepth==0) in the which it is slightly smaller by about width(y) slices (one less row on the bottom of the multiplier). Note that the approximate area in CLBs for XC4000 is the approxiamate area in slices for Virtex.

Copyright (c) 1998-2000 Brigham Young University. All rights reserved. Reproduction in whole or in part in any form or medium without express permission of Brigham Young University is prohibited.

Version:

$Revision: 1.3 $

Author:

Russell Fredrickson

Field Summary

static CellInterface[]	cell_interface Standard JHDL CellInterface.
static boolean	disableWarning Field that will turn off the warning message that is given when the width of the y input is greater than the width of the x input in a pipelined multiplier.
static int	SIGNED definition of SIGNED used in arrayMult
static int	UNSIGNED definition of UNSIGNED used in arrayMult
static boolean	verbose Field to turn on verbose creation of multipliers (tells the size of the multiplier, whether is is signed or not and the pipedepth).

Fields inherited from class byucc.jhdl.Logic.Logic

ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF

Fields inherited from class byucc.jhdl.Logic.LogicGates

tech_mapper

Fields inherited from class byucc.jhdl.base.Cell

BOOLEAN, CELL_NAME_DECLARATION, CellInterfaceDeterminesUniqueNetlistStructure, DETERMINE_FROM_STRING, GENERICS_DECLARATION, implicit_interface, IMPLICIT_INTERFACE_DECLARATION, INTEGER, INTERFACE_DECLARATION, LONG, PORT_IOS_DECLARATION, PORT_NAMES_DECLARATION, PORT_NET_NAMES_DECLARATION, PORT_PROPERTIES, PORT_WIDTHS_DECLARATION, SIGN_EXT, STRING, ZERO_PAD

Fields inherited from interface byucc.jhdl.base.BooleanFlags

ANTECEDANT_IS_BEHAVIORALLY_MODELED, ASYNC_PORT, ASYNCHRONOUS_RESOLVED, ATOMICALLY_PLACEABLE, ATOMICALLY_UNMAPPABLE, BEHAVIORALLY_MODELED_BRANCH, CLK_PORT, CLOCK_METHOD_IMPLEMENTED_BY_USER, CLOCK_METHOD_IS_DISABLED, CLOCKABLE_IS_SCHEDULED, DANGLING_IS_OK, DELETE_MARK, FATAL_BUILD_ERROR_OCCURED, HAS_BEEN_TRACED, HAS_USER_SPECIFIED_NAME, HWUPDATE, IMPLICIT_PORT, IN_CLK_PORT, IN_PORT, INOUT_PORT, IO_TYPE_FLAGS, IS_BEHAVIORALLY_MODELED, IS_ON_BUILD_STACK, IS_ON_PROP_LIST, IS_PLACED, METHODS_IMPLEMENTED_BY_USER, NETLISTABLE, ORIG_WIRE_IS_ATOMIC, OUT_PORT, PLACEMENT_IS_LOCKED, PROPAGATE_METHOD_IMPLEMENTED_BY_USER, PROPAGATE_METHOD_IS_DISABLED, RECURSION_FLAG, RESET_METHOD_IMPLEMENTED_BY_USER, SIMULATEABLE, SOURCELESS_IS_OK, SYNC_PORT, VISIBLE

Constructor Summary

arrayMult(Node parent, Wire x, Wire y, Wire clk_en, Wire pout, int sign, int pipedepth)
Constructor without an instance name parameter.

arrayMult(Node parent, Wire x, Wire y, Wire clk_en, Wire pout, int sign, int pipedepth, java.lang.String instanceName)
Constructor with an instance name parameter.

Method Summary

boolean	cellInterfaceDeterminesUniqueNetlistStructure() Method to indicate that the netlister can assume that the wires and the bound parameters in the cell interface uniquely determine a cell structure.
void	clock() Clock method is used for behavioral pipelined similuation.
static long	compute(long x, int lx, long y, int ly, int lp, int sign) Compute method will provide a mathematically correct answer to what the multiplier would compute with the given parameters and inputs.
boolean	defaultSimulationModelIsBehavioral() The default simulation model is behavioral.
int	getLatency() Method to get the latency of a multiplier is already constructed.
int	getNumOfStages() Method to get the number of pipelinable logic stages of a multiplier that is already constructed.
void	initUserDefinedNode(UserDefinedNode udn) init method needed for UserDefinedSchematic interface.
static int	latency(int yWidth, boolean virtexMult, int pipedepth) The latency method gives the latency in clock cycles of the module with the given input parameters.
static int	numOfStages(int yWidth, boolean virtexMult) Method that calculates the number of pipelinable logic stages (stages consist of mulitplier/adder units).
void	paint(UserDefinedNode udn) paint method for UserDefinedSchematic interface.
void	propagate() Propagate method for combinational behavioral simulation (no registers).
void	reset() Reset method simply puts zeros onto pout wire and clears behavioral delay array.

Methods inherited from class byucc.jhdl.Logic.Logic

clockDriver, clockDriver, connect_implicit_ports, connectImplicitPorts, constructSubCell, constructSubCellNoImplicitPorts, enableNewPlacement, enableNewPlacement, extend, extend, getDefaultClock, getDefaultTechMapper, getGlobalClock, getSinkCell, getSourceCell, getSourceCell, getSourceLeaf, getSourcePlaceable, getSourcePlaceableLeaf, getSubCellClass, getTechMapHint, getTechMapHint, getTechMapper, growAndShiftl, lockChildPlacement, lsb, lsb, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, map, msb, msb, msbIndx, netlist, netlist, netlist, netlist, netlist, netlist, netlist, netlist, padClock_o, padClock_o, padClock_o, padClock, padClock, padClock, padIn_o, padIn_o, padIn_o, padIn, padIn, padIn, padInout_o, padInout_o, padInout_o, padInout, padInout, padInout, padOut_o, padOut_o, padOut_o, padOut, padOut, padOut, padOutT_o, padOutT_o, padOutT_o, padOutT, padOutT, padOutT, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, place, printTechMapHints, range, rotate, rotate, scale, scale, setBBox, setDefaultTechMapper, setFloorPlannerIsMaster, setTechMappingEnabled, setWandH, signExtend_o, signExtend, signExtend, sink, source, takeBot_o, takeBot, takeBot, takeBotSigned_o, takeBotSigned, takeTop_o, takeTop, takeTop, techmap, techMappingEnabled, translate, translate, zeroExtend_o, zeroExtend, zeroExtend, zeroExtendRight_o, zeroExtendRight

Methods inherited from class byucc.jhdl.Logic.LogicStatic

add_o, add_o, and_o, and_o, and, and, buf_o, buf_o, buf, buf, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux, nc, nc, nc, nc, nc, nc, not_o, not_o, not, not, or_o, or_o, or, or, reg_o, reg, vcc_o, vcc_o, vcc, vcc, vcc, vcc, wire, wire, wire, wire, xnor_o, xnor_o, xnor, xor_o, xor

Methods inherited from class byucc.jhdl.Logic.LogicGates

add_o, add_o, add_o, add_o, add_o, add_o, add, add, add, add, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub_o, addsub, addsub, addsub, addsub, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and_o, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, and, ashiftr_o, ashiftr, ashiftr, buf_o, buf_o, buf, buf, checkValueRepresentableInWidth, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat_o, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, concat, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant_o, constant, constant, constant, constant, constant, constant, constant, constant, constant, constant, gnd_o, gnd_o, gnd, gnd, gnd, gnd, mux_o, mux_o, mux_o, mux_o, mux_o, mux_o, mux, mux, mux, mux, mux, mux, name, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand_o, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nand, nc, nc, nc, nc, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor_o, nor, nor, nor, nor, nor, nor, nor,