|
|||||||||||
| PREV CLASS NEXT CLASS | FRAMES NO FRAMES | ||||||||||
| SUMMARY: NESTED | FIELD | CONSTR | METHOD | DETAIL: FIELD | CONSTR | METHOD | ||||||||||
java.lang.Objectbyucc.jhdl.base.Nameable
byucc.jhdl.base.Node
byucc.jhdl.base.Cell
byucc.jhdl.base.Structural
byucc.jhdl.Logic.LogicGates
byucc.jhdl.Logic.LogicStatic
byucc.jhdl.Logic.Logic
byucc.jhdl.platforms.util.Virtex_IOB
This class is used to create IOBs for the Xilinx Virtex series parts. These pads will both simulate and netlist correctly. There are two main places where this class is designed to be used. Each uses a different constructor. The first use is as a tri-state only pad when netlisting outside of a board model. In this case, it only needs to be used for tri-state pads, as the Virtex Techmapper/netlister will correctly insert pads for in and out ports. This model can also be used for any type of IOB when used in a board model. This version is designed to be used with the rest of the platforms.util package. Please see the documentation for the appropriate constructor for more details.
| Field Summary | |
static CellInterface[] |
cell_interface
Cell Interface for the class. |
| Fields inherited from class byucc.jhdl.Logic.Logic |
ABOVE, ALIGN_BOTTOM, ALIGN_CENTER, ALIGN_LEFT, ALIGN_LSB, ALIGN_MSB, ALIGN_RIGHT, ALIGN_TOP, BELOW, DOWN, EAST_OF, LEFT_OF, MAX_PACK, NORTH_OF, ON, ONTOP, ONTOP_OF, RIGHT_OF, SOUTH_OF, TOLEFT, TORIGHT, UNCONSTRAINED, UP, WEST_OF |
| Fields inherited from class byucc.jhdl.Logic.LogicGates |
tech_mapper |
| Constructor Summary | |
Virtex_IOB(Node parent,
VirtualPort vp,
Wire in,
Wire out,
Wire pad,
java.lang.String name)
Constructor used for board models. |
|
Virtex_IOB(Node parent,
Wire in,
Wire out,
Wire out_enable,
Wire pad,
java.lang.String name,
boolean outreg,
boolean inreg,
java.lang.String slewrate)
Constructor used outside of board models. |
|