A B C D E F G H I J K L M N O P Q R S T U V W X Y Z _

R

R0 - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

R180 - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

R270 - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

R90 - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RADIAN - Static variable in class byucc.jhdl.Logic.Modules.Cordic

RADIAN - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.End_rot

RADIAN - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Init_rot

RADIAN - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Stage

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.Cordic

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.End_rot

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Init_rot

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Stage

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.CordicRP

RADIAN - Static variable in class byucc.jhdl.contrib.modgen.StageRP

RADIX_FORMAT_LIST - Static variable in class byucc.jhdl.apps.Viewers.Schematic.SchematicViewerPanel

RADIX_NAME_LIST - Static variable in class byucc.jhdl.apps.Viewers.Schematic.SchematicViewerPanel

Used to support the JComboBox for radix selection

RAM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

RAM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

RAM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

RAM16X1D - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates that a ram16x1d is located in the slice.

RAM16X1D - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates that a ram16x1d is located in the slice.

RAM16X1F - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates that a ram16x1s/srl16(e) is located in the F LUT.

RAM16X1F - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates that a ram16x1s/srl16(e) is located in the F LUT.

RAM16X1G - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates that a ram16x1s/srl16(e) is located in the G LUT.

RAM16X1G - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates that a ram16x1s/srl16(e) is located in the G LUT.

RAM32X1 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates that a ram32x1s is located in the slice.

RAM32X1 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates that a ram32x1s is located in the slice.

RAMB16 - class byucc.jhdl.Xilinx.Virtex2.RamPack.RAMB16.

This class provides the functionality of the RAMB16 Virtex2 library elements.

RAMB16(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RamPack.RAMB16

RAMB16(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RamPack.RAMB16

RAMB16(Node, String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RamPack.RAMB16

RAMB16Dual - class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual.

Deprecated. Use RAMB16_S_S instead.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with parity port on port B.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String, boolean) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Dual

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16DualNoParity - class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity.

Deprecated. Use RAMB16_S_S instead.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16DualNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualNoParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16DualParity - class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity.

Deprecated. Use RAMB16_S_S instead.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16DualParityB - class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB.

Deprecated. Use RAMB16_S_S instead.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported Block RAM with parity port.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM with dual parity ports.

RAMB16DualParityB(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16DualParityB

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16Single - class byucc.jhdl.Xilinx.Virtex2.RAMB16Single.

Deprecated. Use RAMB16_S instead.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new single-ported Block RAM with clock.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new single-ported Block RAM with parity.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16Single

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16SingleNoParity - class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity.

Deprecated. Use RAMB16_S instead.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new single-ported Block RAM with clock.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new named, single-ported Block RAM.

RAMB16SingleNoParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleNoParity

Deprecated. Constructs a new, named single-ported Block RAM with clock.

RAMB16SingleParity - class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity.

Deprecated. Use RAMB16_S instead.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new single-ported Block RAM with parity.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new dual-ported, multi-clock Block RAM.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16SingleParity(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16SingleParity

Deprecated. Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S - class byucc.jhdl.Xilinx.Virtex2.RAMB16_S.

This class provides the functionality of the RAMB16_Sn Virtex2 library elements - The Single-ported BlockRams.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new named, single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new named, single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new named, single-ported Block RAM.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

Constructs a new, named single-ported Block RAM with clock.

RAMB16_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[], String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S

RAMB16_S_S - class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S.

This class provides the functionality of the RAMB16_Sn_Sn Virtex2 library elements - The Dual-ported BlockRams.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, long[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[], String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[], String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[], String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB16_S_S(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.RAMB16_S_S

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB4Dual - class byucc.jhdl.Xilinx.Virtex.RAMB4Dual.

This class provides the functionality of the RAMB4_Sn_Sn Virtex library elements.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

Constructs a new named, dual-ported, multi-clock Block RAM.

RAMB4Dual(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual

RAMB4Dual_rb - class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb.

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Dual_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Dual_rb

RAMB4Single - class byucc.jhdl.Xilinx.Virtex.RAMB4Single.

This class provides the functionality of the RAMB4_Sn Virtex library elements.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new single-ported Block RAM with clock.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new, named single-ported Block RAM with clock.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new, named single-ported Block RAM with clock.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new named, single-ported Block RAM.

RAMB4Single(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

Constructs a new, named single-ported Block RAM with clock.

RAMB4Single(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single

RAMB4Single_rb - class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb.

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4Single_rb(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int[], String) - Constructor for class byucc.jhdl.Xilinx.Virtex.RAMB4Single_rb

RAMB4_Dual - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Dual.

This class provides the functionality of the RAMB4_Sn_Sn Virtex library elements for EDIF parsing only.

RAMB4_Dual(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Dual

RAMB4_Single - class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Single.

This class provides the functionality of the RAMB4_Sn Virtex library elements for EDIF parsing only.

RAMB4_Single(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ramb4_wrapper.RAMB4_Single

RAMLoc - Variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates what RAM resources are used in the block.

RAMLoc - Variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates what RAM resources are used in the block.

RAMType - Variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.Block

Indicates what types RAMs are implemented by the block.

RAMType - Variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Block

Indicates what types RAMs are implemented by the block.

RAM_DATA_SIZE - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack.LookupTableBlockRAM

RAM_DATA_WIDTH - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack.LookupTableBlockRAM

RAM_FRAME_COUNT - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexBitstreamParams

Block RAM frame count from XAPP 138, the same for all devices

RAM_FRAME_COUNT - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Virtex2BitstreamParams

Block RAM frame count from XAPP 138, the same for all devices

RAM_PARITY_WIDTH - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDividePack.LookupTableBlockRAM

RANGEVECTOR - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

RANGLE - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

RBLocation - class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation.

This class is used to keep track of the location of a symbol (flip-flop or RAM) in the readback bitstream.

RBLocation() - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation

Constructs an object, setting the frame and frameOffset to the illegal values of -1

RBLocation(RBLocation) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation

Constructs an object, copying the values of an existing RBLocation object to the new object.

RBLocation(int, int) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation

Deprecated. See RBLocation.RBLocation(int,int,int)

RBLocation(int, int, int) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.RBLocation

Constructs an object by directly setting the frame and frame offset based on its parameters.

RBLocation - class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation.

This class is used to keep track of the location of a symbol (flip-flop or RAM) in the readback bitstream.

RBLocation() - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation

Constructs an object, setting the frame and frameOffset to the illegal values of -1

RBLocation(RBLocation) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation

Constructs an object, copying the values of an existing RBLocation object to the new object.

RBLocation(int, int) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation

Deprecated. See RBLocation.RBLocation(int,int,int)

RBLocation(int, int, int) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.RBLocation

Constructs an object by directly setting the frame and frame offset based on its parameters.

RBR - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

RBRACKET - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

RBRACKET - Static variable in interface byucc.jhdl.util.BVFormat.FormatStringParserConstants

RB_FAILURE - Static variable in interface byucc.jhdl.platforms.util.readback.NativeReadBackInterface

Constant indicating the failure of an operation

RB_FAILURE - Static variable in interface byucc.jhdl.platforms.util.readback.NativeReadWriteBackInterface

Constant indicating the failure of an operation

RB_POSTAMBLE_SIZE - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XC4KBitstreamParams

The size of one start bit and 11 CRC bits

RB_SUCCESS - Static variable in interface byucc.jhdl.platforms.util.readback.NativeReadBackInterface

Constant indicating the success of an operation

RB_SUCCESS - Static variable in interface byucc.jhdl.platforms.util.readback.NativeReadWriteBackInterface

Constant indicating the success of an operation

READ_FIRST - Static variable in class byucc.jhdl.Xilinx.Virtex2.RamPack.BlockRamView

READ_FIRST - Static variable in class byucc.jhdl.Xilinx.Virtex2.RamPack.BlockRamViewL

RECTANGLE - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RECTANGLESIZE - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RECURSION_FLAG - Static variable in interface byucc.jhdl.base.BooleanFlags

Whether a wire has been visited during a recursive trace

REDUNDANTBLOCKS - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

REDUNDANTBLOCKS - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

REDUNDANTBLOCKS - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.Logic.Modules.MultArrayPack.multCol

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack.multCol

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack.multCol

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack.multCol

REGISTER_ADD_OUT - Static variable in class byucc.jhdl.contrib.modgen.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.Logic.Modules.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack.multCol

REGISTER_NOTHING - Static variable in class byucc.jhdl.contrib.modgen.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.Logic.Modules.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack.multCol

REGISTER_X - Static variable in class byucc.jhdl.contrib.modgen.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.Logic.Modules.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.Xilinx.XC4000.Modules.MultArrayPack.multCol

REGISTER_YSUM - Static variable in class byucc.jhdl.contrib.modgen.MultArrayPack.multCol

REMAINDER_INDEX - Static variable in class byucc.jhdl.Logic.Modules.IntDivide

For indexing the remainder in the 3 element array compute() returns

REMAINDER_INDEX - Static variable in class byucc.jhdl.contrib.modgen.IntDivide

For indexing the remainder in the 3 element array compute returns

REMOVED - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

REMOVED - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

REMOVED - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

RENAME - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

REQUIRED - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RESET - Static variable in class byucc.jhdl.apps.Broker.BrokerCmds

RESET - Static variable in class byucc.jhdl.apps.Viewers.SimControl.SimControlActionEvent

RESET_METHOD_IMPLEMENTED_BY_USER - Static variable in interface byucc.jhdl.base.BooleanFlags

Records whether the Structural.reset() method of a Structural cell is implemented by the use.

RESISTANCE - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

RESOLVES - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

REVISION - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

REVISION - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

REVISION - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

RIGHT - Static variable in class byucc.jhdl.CSRC.Shifter

Simple flag for identifying the right-shift direction in the constructor call.

RIGHT - Static variable in class byucc.jhdl.TERA.Shifter

Simple flag for identifying the right-shift direction in the constructor call.

RIGHT - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.Shifter

RIGHT - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.Shifter

RIGHT - Static variable in class byucc.jhdl.Xilinx.XC4000.Shifter

Simple flag for identifying the right-shift direction in the constructor call.

RIGHT - Static variable in class byucc.jhdl.Xilinx.XC9000.Modules.Shifter

RIGHT_OF - Static variable in class byucc.jhdl.Logic.Logic

Relational Placement directive which indicates that the current cell should be placed in the positive X direction on the JHDL grid from a previous cell.

RIPPER - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

ROM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexConstants

ROM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2Constants

ROM - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KConstants

ROM_ADDR_BITS - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.KCMMult

ROM_ADDR_BITS - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack.KCMRom_Adder

ROM_ADDR_BITS - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.KCM_Pack.KCM_ROM

ROM_BITS - Static variable in class byucc.jhdl.Xilinx.Virtex.Modules.KCMMult

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.Cordic

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Cordic_ctrl

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.End_rot

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Init_rot

ROTATIONAL - Static variable in class byucc.jhdl.Logic.Modules.CordicPack.Stage

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.Cordic

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Cordic_ctrl

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Cordicl_ctrl

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.End_rot

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Init_rot

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Stage

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicPack.Stagel

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.CordicRP

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.Cordicl

ROTATIONAL - Static variable in class byucc.jhdl.contrib.modgen.StageRP

ROUND - Static variable in interface byucc.jhdl.parsers.edif.EdifParserCoreConstants

ROUND_TOWARD_ZERO - Static variable in class byucc.jhdl.Logic.Modules.FloatingPoint.FPDivide

A constant for truncation mode (no rounding).

ROUND_TOWARD_ZERO - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDivide

A constant for truncation mode (no rounding).

ROUND_TO_NEAREST - Static variable in class byucc.jhdl.Logic.Modules.FloatingPoint.FPDivide

A constant for the default rounding mode: Round to nearest.

ROUND_TO_NEAREST - Static variable in class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPDivide

A constant for the default rounding mode: Round to nearest.

ROW_COUNT_XC2S100 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S15 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S150 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S200 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S30 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XC2S50 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV100 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV1000 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV150 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV200 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV300 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV400 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV50 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

The row count for the different part types

ROW_COUNT_XCV600 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

ROW_COUNT_XCV800 - Static variable in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressBitstreamParams

RPARAN - Static variable in interface byucc.jhdl.util.BVFormat.FormatStringParserConstants

RPAREN - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexConstants

RPAREN - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2Constants

RPAREN - Static variable in interface byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KConstants

RULES_ONLY - Static variable in class byucc.jhdl.DRC.DesignRuleBrowser

Ram(int, int, int, String) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

Parses the "Ram=..." clauses of the RAM LL entries and enters the data into the RAMGroupHash.

Ram(int, int, int, String) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

Parses the "Ram=..." clauses of the RAM LL entries and enters the data into the RAMGroupHash.

Ram(int, int, int, String) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

Parses the "Ram=..." clauses of the RAM LL entries and enters the data into the RAMGroupHash.

Random - class byucc.jhdl.apps.Stimulator.functions.Random.

This class implements the ValueProvider interface to provide a random value for wire stimulus.

Random(long) - Constructor for class byucc.jhdl.apps.Stimulator.functions.Random

Creates a new Random ValueProvider that uses the given value as a seed for the random values.

Random() - Constructor for class byucc.jhdl.apps.Stimulator.functions.Random

Creates a new Random ValueProvider that uses the current time as the seed for the random values.

Range() - Method in class byucc.jhdl.util.BVFormat.FormatStringParser

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.Fsm.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.Fsm.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.Fsm.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.Fsm.ASCII_CharStream

ReInit(InputStream) - Method in class byucc.jhdl.Fsm.Parser

ReInit(Reader) - Method in class byucc.jhdl.Fsm.Parser

ReInit(ParserTokenManager) - Method in class byucc.jhdl.Fsm.Parser

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.Fsm.ParserTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.Fsm.ParserTokenManager

ReInit(Reader, int, int, int) - Static method in class byucc.jhdl.base.genericparser.ASCII_CharStream

ReInit(Reader, int, int) - Static method in class byucc.jhdl.base.genericparser.ASCII_CharStream

ReInit(InputStream, int, int, int) - Static method in class byucc.jhdl.base.genericparser.ASCII_CharStream

ReInit(InputStream, int, int) - Static method in class byucc.jhdl.base.genericparser.ASCII_CharStream

ReInit(InputStream) - Static method in class byucc.jhdl.base.genericparser.exprParser

ReInit(Reader) - Static method in class byucc.jhdl.base.genericparser.exprParser

ReInit(exprParserTokenManager) - Method in class byucc.jhdl.base.genericparser.exprParser

ReInit(ASCII_CharStream) - Static method in class byucc.jhdl.base.genericparser.exprParserTokenManager

ReInit(ASCII_CharStream, int) - Static method in class byucc.jhdl.base.genericparser.exprParserTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.parsers.edif.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.parsers.edif.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.parsers.edif.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.parsers.edif.ASCII_CharStream

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.parsers.edif.EdifParserCoreTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.parsers.edif.EdifParserCoreTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.ASCII_CharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

ReInit(LL_VirtexTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexTokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_VirtexTokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

ReInit(MRP_VirtexTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexTokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_VirtexTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_Virtex

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_Virtex

ReInit(XDL_VirtexTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_Virtex

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_VirtexTokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.XDL_VirtexTokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

ReInit(LL_Virtex2TokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2TokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2TokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

ReInit(MRP_Virtex2TokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2TokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2TokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2

ReInit(XDL_Virtex2TokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2

ReInit(SimpleCharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2TokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.XDL_Virtex2TokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.ASCII_CharStream

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

ReInit(LL_4KTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4KTokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

ReInit(MRP_4KTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4KTokenManager

ReInit(InputStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4K

ReInit(Reader) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4K

ReInit(XDL_4KTokenManager) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4K

ReInit(ASCII_CharStream) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4KTokenManager

ReInit(ASCII_CharStream, int) - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XDL_4KTokenManager

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.synth.graph.parser.ASCII_UCodeESC_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.synth.graph.parser.ASCII_UCodeESC_CharStream

ReInit(InputStream) - Static method in class byucc.jhdl.synth.graph.parser.DotFileParser

ReInit(DotFileParserTokenManager) - Method in class byucc.jhdl.synth.graph.parser.DotFileParser

ReInit(ASCII_UCodeESC_CharStream) - Static method in class byucc.jhdl.synth.graph.parser.DotFileParserTokenManager

ReInit(ASCII_UCodeESC_CharStream, int) - Static method in class byucc.jhdl.synth.graph.parser.DotFileParserTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.util.BVFormat.ASCII_CharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.util.BVFormat.ASCII_CharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.util.BVFormat.ASCII_CharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.util.BVFormat.ASCII_CharStream

ReInit(InputStream) - Method in class byucc.jhdl.util.BVFormat.FormatStringParser

ReInit(Reader) - Method in class byucc.jhdl.util.BVFormat.FormatStringParser

ReInit(FormatStringParserTokenManager) - Method in class byucc.jhdl.util.BVFormat.FormatStringParser

ReInit(SimpleCharStream) - Method in class byucc.jhdl.util.BVFormat.FormatStringParserTokenManager

ReInit(SimpleCharStream, int) - Method in class byucc.jhdl.util.BVFormat.FormatStringParserTokenManager

ReInit(Reader, int, int, int) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(Reader, int, int) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(Reader) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(InputStream, int, int, int) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(InputStream) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReInit(InputStream, int, int) - Method in class byucc.jhdl.util.BVFormat.SimpleCharStream

ReadBackData - class byucc.jhdl.platforms.util.readback.ReadBackData.

The class provides a place for holding all of the information relating to readback for a given PE.

ReadBackDataException - exception byucc.jhdl.platforms.util.readback.ReadBackDataException.

This exception class is used to indicate that various error conditions experienced by the ReadBackData class.

ReadBackManager - class byucc.jhdl.platforms.util.readback.ReadBackManager.

This class provides a testbench (frequently, a board model) with the functionality required to manage readback for a board of contiguously numbered PEs starting with PE 0.

ReadBackManager(NativeReadBackInterface, int) - Constructor for class byucc.jhdl.platforms.util.readback.ReadBackManager

The constructor allocates and initializes the data structures for managing readback for the testbench.

ReadBackManager(NativeReadBackInterface, int, boolean) - Constructor for class byucc.jhdl.platforms.util.readback.ReadBackManager

This is only used by ReadWriteBackManager.

ReadBackSymbolWriter - class byucc.jhdl.platforms.util.readback.Xilinx.ReadBackSymbolWriter.

This class creates the .rbsym "netlist" of all ExternallyUpdateable and LargeExternallyUpdateable objects for Xilinx XC4000 and Virtex FPGAs in JHDL.

ReadBackSymbolWriter(String) - Constructor for class byucc.jhdl.platforms.util.readback.Xilinx.ReadBackSymbolWriter

The constructor essentially prepares an .rbsym file for writing.

ReadRBSymFile(String) - Static method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexToJHDLSyms

Creates a Hashtable of RBSym objects keyed on the state elements' instance names from the design's .rbsym file.

ReadRBSymFile(String) - Static method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.VirtexXpressToJHDLSyms

ReadRBSymFile(String) - Static method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.Virtex2ToJHDLSyms

Creates a Hashtable of RBSym objects keyed on the state elements' instance names from the design's .rbsym file.

ReadRBSymFile(String) - Static method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.XC4KToJHDLSyms

Creates a Hashtable of RBSym objects keyed on the state elements' instance names from the design's .rbsym file.

ReadStateCommand - class byucc.jhdl.apps.Tbone.ReadStateCommand.

ReadStateCommand(Tbone) - Constructor for class byucc.jhdl.apps.Tbone.ReadStateCommand

ReadWriteBackData - class byucc.jhdl.platforms.util.readback.ReadWriteBackData.

The class provides a place for holding all of the information relating to readback and writeback for a given PE.

ReadWriteBackManager - class byucc.jhdl.platforms.util.readback.ReadWriteBackManager.

This class provides a board model with the functionality required to manage readback and writeback for a board of contiguously numbered PEs starting with PE 0.

ReadWriteBackManager(NativeReadWriteBackInterface, int) - Constructor for class byucc.jhdl.platforms.util.readback.ReadWriteBackManager

The constructore allocates and initializes the data structures for managing readback for the board.

Recent_Classes_File - Static variable in class byucc.jhdl.apps.Jab.BrowserCore

Deprecated.

Recent_Format_File - Static variable in class byucc.jhdl.apps.Jab.BrowserCore

Deprecated.

RectToPolar(Node, Wire, Wire, Wire, Wire) - Static method in class byucc.jhdl.Logic.Modules.CORDICS

Recurser - class byucc.jhdl.Xilinx.XC4000.techmap.tree.Recurser.

Recurser() - Constructor for class byucc.jhdl.Xilinx.XC4000.techmap.tree.Recurser

RecursionOperator - class byucc.jhdl.Xilinx.XC4000.techmap.tree.RecursionOperator.

RecursionOperator() - Constructor for class byucc.jhdl.Xilinx.XC4000.techmap.tree.RecursionOperator

RedundantBlocks() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

Parses the Redundant Block subsection of the file.

RedundantBlocks() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

Parses the Redundant Block subsection of the file.

RedundantBlocks() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

Parses the Redundant Block subsection of the file.

Reflection - class byucc.jhdl.apps.util.Reflection.

Class to assist in the some of the reflection work done by classes such as Stimulator and DynamicTestBench

Reflection() - Constructor for class byucc.jhdl.apps.util.Reflection

RegNode - class byucc.jhdl.apps.Viewers.Schematic.RegNode.

RegNode(Cell, SchematicCanvas, int) - Constructor for class byucc.jhdl.apps.Viewers.Schematic.RegNode

RegisterException - exception byucc.jhdl.platforms.util.RegisterException.

RegisterException() - Constructor for class byucc.jhdl.platforms.util.RegisterException

ReleaseCommand - class byucc.jhdl.apps.Tbone.ReleaseCommand.

ReleaseCommand(Tbone) - Constructor for class byucc.jhdl.apps.Tbone.ReleaseCommand

Remainder - class byucc.jhdl.Logic.Modules.FloatingPoint.SqPack.Remainder.

General Description

Remainder(Node, Wire, Wire) - Constructor for class byucc.jhdl.Logic.Modules.FloatingPoint.SqPack.Remainder

Remainder(Node, Wire, Wire, String) - Constructor for class byucc.jhdl.Logic.Modules.FloatingPoint.SqPack.Remainder

RemoteDataReturn - class byucc.jhdl.platforms.util.hwi.RemoteDataReturn.

RemoteDataReturn() - Constructor for class byucc.jhdl.platforms.util.hwi.RemoteDataReturn

RemoteDataReturn(int, byte[][], byte[]) - Constructor for class byucc.jhdl.platforms.util.hwi.RemoteDataReturn

RemoteHardwareControl - class byucc.jhdl.platforms.util.hwi.RemoteHardwareControl.

RemoteHardwareControl(HardwareControlInterface) - Constructor for class byucc.jhdl.platforms.util.hwi.RemoteHardwareControl

RemovedBlock() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

Parses just the removed logic/block clauses for the Trimmed Logic section.

RemovedBlock() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

Parses just the removed logic/block clauses for the Trimmed Logic section.

RemovedBlock() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

Parses just the removed logic/block clauses for the Trimmed Logic section.

RemovedSignal() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.MRP_Virtex

Parses just the removed signal clauses for the Trimmed Logic section.

RemovedSignal() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.MRP_Virtex2

Parses just the removed signal clauses for the Trimmed Logic section.

RemovedSignal() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.MRP_4K

Parses just the removed signal clauses for the Trimmed Logic section.

Reset - Static variable in class byucc.jhdl.apps.Jab.KeyMan

ResetCommand - class byucc.jhdl.apps.Tbone.ResetCommand.

ResetCommand(HWSystem) - Constructor for class byucc.jhdl.apps.Tbone.ResetCommand

ResetParser - class byucc.jhdl.util.xmac.ResetParser.

Parse the reset tag.

ResetParser(DocInfo) - Constructor for class byucc.jhdl.util.xmac.ResetParser

The default constructor for this class.

Reverse - class byucc.jhdl.Logic.Modules.Reverse.

Completely reverses (mirrors) the bit order of the input, so that LSB becomes MSB, etc...

Reverse(Node, Wire, Wire) - Constructor for class byucc.jhdl.Logic.Modules.Reverse

every output is reversed order of the input, i.e.

ReversePriorityEncoder - class byucc.jhdl.Xilinx.Virtex.Modules.ReversePriorityEncoder.

encodes the input value, prioritizing the bits by LSB has highest priority.

ReversePriorityEncoder(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ReversePriorityEncoder

ReversePriorityEncoder(Node, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ReversePriorityEncoder

"Active" output is removed, for performance reasons.

ReversePriorityEncoder - class byucc.jhdl.Xilinx.Virtex2.Modules.ReversePriorityEncoder.

encodes the input value, prioritizing the bits by LSB has highest priority.

ReversePriorityEncoder(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ReversePriorityEncoder

ReversePriorityEncoder(Node, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.ReversePriorityEncoder

"Active" output is removed, for performance reasons.

ReversedDepthFirstAdapter - class byucc.jhdl.parsers.edif.sablecc.analysis.ReversedDepthFirstAdapter.

ReversedDepthFirstAdapter() - Constructor for class byucc.jhdl.parsers.edif.sablecc.analysis.ReversedDepthFirstAdapter

Revision() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

Parses the revision information for the .ll file.

Revision() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

Parses the revision information for the .ll file.

Revision() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

Parses the revision information for the .ll file.

RightShiftReg - class byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack.RightShiftReg.

RightShiftReg.java Created: 3/2002

RightShiftReg(Node, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.Modules.ShiftReg_Pack.RightShiftReg

Rom() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex.LL_Virtex

Parses "Rom=..." entries, but doesn't do anything with them.

Rom() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.Virtex2.LL_Virtex2

Parses "Rom=..." entries, but doesn't do anything with them.

Rom() - Method in class byucc.jhdl.platforms.util.readback.Xilinx.XC4000.LL_4K

Parses "Rom=..." entries, but doesn't do anything with them.

Rom128x1View - class byucc.jhdl.Xilinx.Virtex2.Rom128x1View.

This class is for the simulation of block ram's to work correctly.

Rom128x1View(Node, Wire, Wire, String, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Rom128x1View

Rom256x1View - class byucc.jhdl.Xilinx.Virtex2.Rom256x1View.

This class is for the simulation of block ram's to work correctly.

Rom256x1View(Node, Wire, Wire, String, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Rom256x1View

Rom64x1View - class byucc.jhdl.Xilinx.Virtex2.Rom64x1View.

This class is for the simulation of block ram's to work correctly.

Rom64x1View(Node, Wire, Wire, String, int[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Rom64x1View

Round - class byucc.jhdl.Logic.Modules.FloatingPoint.FPAddSubPack.Round.

Round(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int, int) - Constructor for class byucc.jhdl.Logic.Modules.FloatingPoint.FPAddSubPack.Round

Round - class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack.Round.

Round(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, int, int) - Constructor for class byucc.jhdl.Xilinx.Virtex2.Modules.FloatingPoint.FPAddSubPack.Round

RoundPipe_IntDivide(Node, Wire, Wire, Wire, Wire, int) - Static method in class byucc.jhdl.Logic.Modules.DIVIDERS

RoundPipe_IntDivide(Node, Wire, Wire, Wire, Wire, int, String) - Static method in class byucc.jhdl.Logic.Modules.DIVIDERS

Round_IntDivide(Node, Wire, Wire, Wire, Wire) - Static method in class byucc.jhdl.Logic.Modules.DIVIDERS

Round_IntDivide(Node, Wire, Wire, Wire, Wire, String) - Static method in class byucc.jhdl.Logic.Modules.DIVIDERS

Rounder(Node, Wire, Wire) - Static method in class byucc.jhdl.Logic.Modules.OTHERS

Rounder(Node, Wire, Wire, String) - Static method in class byucc.jhdl.Logic.Modules.OTHERS

rCompound() - Static method in class byucc.jhdl.synth.graph.parser.DotFileParser

rCompound - class byucc.jhdl.synth.graph.parser.syntaxtree.rCompound.

Grammar production: f0 -> edgeOp() f1 -> simple() f2 -> ( edgeOp() simple() )*

rCompound(edgeOp, simple, NodeListOptional) - Constructor for class byucc.jhdl.synth.graph.parser.syntaxtree.rCompound

radix - Static variable in class byucc.jhdl.apps.Viewers.Schematic.CircuitView

radixFormat - Variable in class byucc.jhdl.apps.Viewers.Schematic.CircuitView

radixFormat - Variable in class byucc.jhdl.apps.Viewers.Schematic.SchematicCanvas

This is the BVFormat that will format the values on the wires of the schematic viewer

ram(Cell, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.CSRC.CSRCTechMapper

ram(Cell, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC4000.XC4000TechMapper

ram(Cell, Wire, Wire, Wire, Wire, long[], String) - Method in class byucc.jhdl.Xilinx.XC9000.XC9000TechMapper

ram128x1s - class byucc.jhdl.Xilinx.Virtex2.ram128x1s.

RAM128X1S is a 128-word by 1-bit static random access memory with synchronous write capability.

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

ram128x1s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Used only by child classes to pass up the parent cell.

ram128x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Used only by child classes to pass up the parent cell and instance name.

ram128x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s.

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram128x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s

Constructs a new ram128x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram128x1s_1 - class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1.

RAM128X1S_1 is a 64-word by 1-bit static random access memory with synchronous write capability.

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

ram128x1s_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Used only by child classes to pass up the parent cell.

ram128x1s_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Used only by child classes to pass up the parent cell and instance name.

ram128x1s_1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1.

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram128x1s_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram128x1s_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram128x1s_1

Constructs a new ram128x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1 - class byucc.jhdl.Xilinx.XC4000.ram16x1.

RAM16X1 is a 16-word by 1-bit static RAM.

ram16x1(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Used only by child classes to pass up the parent cell.

ram16x1(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Used only by child classes to pass up the parent cell and instance name.

ram16x1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1.

ram16x1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1.

ram16x1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1.

ram16x1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1.

ram16x1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1

Constructs a new ram16x1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d - class byucc.jhdl.Xilinx.Virtex.ram16x1d.

RAM16X1D is a 16-word by 1-bit static dual-ported RAM.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

ram16x1d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Used only by child classes to pass up the parent cell.

ram16x1d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Used only by child classes to pass up the parent cell and instance name.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d - class byucc.jhdl.Xilinx.Virtex2.ram16x1d.

RAM16X1D is a 16-word by 1-bit static dual-ported RAM.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

ram16x1d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Used only by child classes to pass up the parent cell.

ram16x1d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Used only by child classes to pass up the parent cell and instance name.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d - class byucc.jhdl.Xilinx.XC4000.ram16x1d.

RAM16X1D is a 16-word by 1-bit static dual-ported RAM.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

ram16x1d(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Used only by child classes to pass up the parent cell.

ram16x1d(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Used only by child classes to pass up the parent cell and instance name.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1d

Constructs a new ram16x1d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d_1 - class byucc.jhdl.Xilinx.Virtex.ram16x1d_1.

RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

ram16x1d_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Used only by child classes to pass up the parent cell.

ram16x1d_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Used only by child classes to pass up the parent cell and instance name.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1d_1

Constructs a new ram16x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d_1 - class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1.

RAM16X1D_1 is a 16-word by 1-bit static dual port random access memory with synchronous write capability and negative-edge clock.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

ram16x1d_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Used only by child classes to pass up the parent cell.

ram16x1d_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Used only by child classes to pass up the parent cell and instance name.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1d_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1d_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1d_1

Constructs a new ram16x1d_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s - class byucc.jhdl.Xilinx.Virtex.ram16x1s.

RAM16X1S is a synchronous 16-word by 1-bit static RAM.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

ram16x1s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Used only by child classes to pass up the parent cell.

ram16x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Used only by child classes to pass up the parent cell and instance name.

ram16x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s - class byucc.jhdl.Xilinx.Virtex2.ram16x1s.

RAM16X1S is a synchronous 16-word by 1-bit static RAM.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

ram16x1s(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Used only by child classes to pass up the parent cell.

ram16x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Used only by child classes to pass up the parent cell and instance name.

ram16x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s - class byucc.jhdl.Xilinx.XC4000.ram16x1s.

RAM16X1S is a synchronous 16-word by 1-bit static RAM.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

ram16x1s(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Used only by child classes to pass up the parent cell.

ram16x1s(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Used only by child classes to pass up the parent cell and instance name.

ram16x1s(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x1s

Constructs a new ram16x1s, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s_1 - class byucc.jhdl.Xilinx.Virtex.ram16x1s_1.

RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

ram16x1s_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Used only by child classes to pass up the parent cell.

ram16x1s_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Used only by child classes to pass up the parent cell and instance name.

ram16x1s_1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x1s_1

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s_1 - class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1.

RAM16X1S_1 is a 16-word by 1-bit static random access memory with synchronous write capability and negative-edge clock.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

ram16x1s_1(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Used only by child classes to pass up the parent cell.

ram16x1s_1(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Used only by child classes to pass up the parent cell and instance name.

ram16x1s_1(Node, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, Wire, Wire, Wire, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x1s_1(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x1s_1(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x1s_1

Constructs a new ram16x1s_1, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d - class byucc.jhdl.Xilinx.Virtex.ram16x2d.

RAM16X2D is a 16-word by 2-bit static dual-ported RAM.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

ram16x2d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Used only by child classes to pass up the parent cell.

ram16x2d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Used only by child classes to pass up the parent cell and instance name.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d - class byucc.jhdl.Xilinx.Virtex2.ram16x2d.

RAM16X2D is a 16-word by 2-bit static dual-ported RAM.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

ram16x2d(Node) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Used only by child classes to pass up the parent cell.

ram16x2d(Node, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Used only by child classes to pass up the parent cell and instance name.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The final String parameters set the generics , INIT_00, INIT_01

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter The initial String parameter specifies the instance name.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, String) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting each Wire to the port whose name is given by the accompanying String parameter Note: this includes enough wires for the implicit ports.

ram16x2d(Node, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d(Node, String, ArgBlockList) - Constructor for class byucc.jhdl.Xilinx.Virtex2.ram16x2d

Constructs a new ram16x2d, connecting its ports as given by the String-Wire pairs in the ArgBlockList.

ram16x2d - class byucc.jhdl.Xilinx.XC4000.ram16x2d.

RAM16X2D is a 16-word by 2-bit static dual-ported RAM.

ram16x2d(Node, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String[]) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

ram16x2d(Node, String, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire, String, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

ram16x2d(Node) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Used only by child classes to pass up the parent cell.

ram16x2d(Node, String) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Used only by child classes to pass up the parent cell and instance name.

ram16x2d(Node, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.ram16x2d

Constructs a new ram16x2d.

ram16x2d(Node, String, Wire, Wire, Wire, Wire, Wire, Wire) - Constructor for class byucc.jhdl.Xilinx.XC4000.