Generally complex module generators consist of two major parts: a front-end that performs data processing to determine the structural circuit details based on some user specification, and a back-end that performs circuit generation and emits the corresponding net-list.
Except in cases where the module generator is extremely simple, the software for the front-end is much better suited to a general-purpose language than a Hardware Description Language (HDL) such as VHDL. Front-end processing ususally interprets user input and this often requires the sort of processing normally associated with a general-purpose language: parsing of input, error detection, construction and processing of dynamic data structures such as linked lists and file I/O, etc.
Moreover, software development is much easier when done with standard compilers and debuggers than with VHDL synthesizers and simulators.
The only way to overcome this problem with VHDL is to take a combined strategy that uses a general-purpose language such as C++ for front-end processing and a VHDL synthesis tool as the back-end for circuit generation. However this approach is unsatisfactory for several reasons:
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Last updated on 11 May 2006